1. Field of the Invention
The present invention relates to a doubled timing synchronous system, and more particularly, to a timing signal supplying device in a doubled timing synchronous system which can correct a timing error in an external input timing signal and in a timing signal inputted to a timing signal receiving circuit.
2. Discussion of Related Art
Generally, a timing signal is transmitted to a base station or terminal device to ensure synchronization of input/output data to and from transmitting/receiving sides in a mobile communication system.
FIG. 1 is a schematic block diagram illustrating a representative doubled timing synchronous system, and FIG. 2 is a block diagram illustrating a timing signal supplying device of FIG. 1.
Referring to FIG. 1, a conventional doubled timing synchronous system inputs a timing signal generated in a timing signal generator (not shown), with a clock signal, to a timing signal supplying circuit 1 and then the timing signal synchronized according to the clock signal is outputted to a plurality of timing signal receiving circuits 11.
Referring to FIG. 2, a conventional timing signal supplying device includes a phase locked loop (hereinafter simply referred to as "PLL") circuit 2 which receives the clock signal generated from a clock generator (not shown) and outputs a predetermined frequency signal; and a transmitting buffer 3 which sequentially transmits the frequency signal from the PLL circuit 2 and an external input timing signal to the timing signal receiving circuit 11.
In operation, the PLL circuit 2 serves to stabilize the clock signal inputted from the exterior and output it as the predetermined frequency signal, and the transmitting buffer 3 serves to transmit the input timing signal and the frequency signal to the timing signal receiving circuit 11.
As shown in FIG. 1, the conventional timing signal supplying device is doubled to supply a stabilized timing signal. Thus, when an enable terminal of the transmitting buffer 3 is in an active state, only an activated timing signal supplying circuit is operated and the other is in a stand-by state.
In the conventional timing signal supplying device, however, even if there occurs timing loss caused due to the separation and operation of the doubled circuit, there is a problem in that the timing signal to be inputted to the transmitting buffer is not synchronous to the timing signal to be inputted to the timing signal receiving circuit.